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Roadmap

Current Status — v6 (GPU / AIPU vector ALU)

Suite Tests Status
Regression (tb_server_dispatch_unit) 15 PASS
MOESI integration (tb_moesi_integration) 3 1 PASS / 2 FAIL — BUG-006 open
Total 18 16 PASS / 2 FAIL

Both results are unchanged from the pre-split v4 baseline — see chiplets.md.

Run both suites: ./run_sims.command

Completed

  • RV32IM assembler (scripts/riscv_asm.py) — real mnemonics, labels, pseudo-ops, and NPU/GPU custom-opcode pseudo-instructions, replacing hand-computed hex in .asm test files. Testbench now always dumps the full register file after halt ([OUTPUT] section), not just checked registers, so a program's actual output is visible without needing assertions. Found and fixed BUG-008 (BLT/BGE/BLTU/BGEU used the wrong ALU op) and BUG-009 (taken branch/JAL/JALR's delay-slot instruction executed once before being flushed) while building the first assembler-generated regression test; also found and fixed BUG-010 and documented (but left open, cosmetic) BUG-011, both instances of hand-encoded hex silently disagreeing with its own comment. See toolchain.md.
  • GPU / AIPU internal micro-architecture — minimum viable 16-lane INT32 vector ALU (ADD/SUB/AND/XOR), restored the previously-reserved NoC routing slot (custom-0, 0x57). See gpu.md.
  • Chiplet disaggregation + UCIe — system_top split into base_die_top / cpu_chiplet_top / npu_chiplet_top, connected by modeled UCIe links (link training + credit-based channels). Found and fixed BUG-007 (halt detection race exposed by decoupling network ingestion from CPU stall). See chiplets.md.
  • RV32IM ALU — MUL (3-cycle), DIV/DIVU/REM/REMU (34-cycle iterative)
  • NoC router replacing SDU — cpu_accept single-pulse write protocol
  • L2 write-back cache — 4-way, 16 sets, 8-word lines, 2 KiB, burst fill
  • NPU INT16 mixed-precision — SET_PREC command, data at [31:18]
  • NPU ping-pong weight banks — SWAP command, zero-bubble tile reuse
  • MOESI coherency controller — 2-master (CPU + NPU DMA), M→S flush
  • MOESI integration testbench — TC-MOESI-1/2/3
  • Structured issue log — docs/issues/

Near-term

  • Fix BUG-006 — TC-MOESI-1/TC-MOESI-2 fail again (NPU DMA reads 0 instead of the CPU-written value) despite the BUG-003 ST_NPU_GAP fix already being present in duck_coherency_ctrl.sv. Needs waveform-level investigation; see docs/issues/BUG-006.md. Roadblocked after two automated runs — parked in docs/unsolved/UNSOLVED-001.md for a human to fix on a branch.
  • GPU vector ALU: more ops — v1 covers ADD/SUB/AND/XOR; a real vector ALU would add OR, shifts, and min/max/compare (useful for future NoC-level reductions).
  • Wireless peripheral driver — packages NPU result frames and transmits to remote displays. Currently a no-op output port.
  • Multi-word NPU DMA — current DMA port reads one word at a time. Extend to burst-load a full weight tile (256 words) in a single DMA transaction.
  • Formal verification of MOESI FSM — use sby (SymbiYosys) to prove the FSM never deadlocks and that npu_dma_ack pulses exactly once per request.
  • MULHSU/MULHU — the only two RV32M instructions the ALU doesn't implement (alu_control is a full 4 bits with all 16 codes already assigned). See reference.md#known-isa-gaps.
  • Disassembler — the inverse of scripts/riscv_asm.py: hex/.hex file → readable assembly with resolved labels, for debugging register-dump output or an unfamiliar .asm fixture without hand-decoding bit fields.
  • ECALL-based console I/O — a couple of syscall numbers in a7 (print-int, print-char) decoded directly in riscv_core.sv's EX stage and surfaced as a new top-level signal (same pattern as the existing halt output), so simple programs can print without touching the memory/coherency path at all. Much lower risk than the MMIO console below — worth doing first.

Medium-term

  • Convolution support in NPU — add im2col pre-processing so the MAC array can be reused for conv layers without software tiling.
  • Out-of-order execution for CPU — scoreboard + register rename for the RV32IM core; needed when DIV latency stalls block shorter downstream instructions.
  • FPGA synthesis target — map pe.sv MAC cells to DSP48 slices on Xilinx/Intel. Add timing constraints and a place-and-route Makefile target.
  • Multi-master DRAM arbiter — right now CPU has strict priority over NPU DMA. Add a fair arbiter (round-robin or weighted) to prevent NPU DMA starvation under heavy CPU miss traffic.
  • Memory-mapped console/UART — a real sw-to-an-address console needs an uncacheable-address range recognized by l2_cache.sv/duck_coherency_ctrl.sv (otherwise a "print" write just sits dirty in the write-back L2 until eviction, instead of being visible immediately). Deferred until BUG-006 — already open in that exact subsystem — is resolved, to avoid compounding an unresolved coherency bug with a new feature in the same code.

Long-term

  • Multi-core CPU cluster — 2–4 RV32IM cores sharing the MOESI L2. Extend duck_coherency_ctrl to a full directory-based protocol (MESI or MESIF) with per-core snoop ports.
  • Full DLA-style pipeline — add conv/pool/activation/normalise stages after the MAC array, inspired by NVDLA's convolution buffer architecture.
  • Network-on-chip (NoC) mesh — replace the current single-router NoC with a 2D mesh topology for multi-tile scaling.
  • OpenLane tape-out — run the RTL through the OpenLane/Sky130 flow to get area, power, and timing numbers on a real process node.