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rtl/npu_chiplet_top.sv — NPU Chiplet

Contains npu (and, inside it, the conceptual pe MAC-cell architecture) and the two UCIe-facing bridge adapters for the NPU link. npu.sv itself is unmodified — this file only wraps it.

Where it fits

Instantiated once by system_top.sv as npu_chiplet_inst, connected to base_die_top over the NPU link's two UCIe channels (npu_disp, npu_result).

Ports

Direction Name Width Description
in clk, rst_n 1, 1 Clock / reset
in disp_rx_valid 1 npu_disp channel rx: dispatch instruction arrived
out disp_rx_ready 1 Wired straight to the NPU's own npu_ready
in disp_rx_data 32 The dispatched NPU instruction word
out res_tx_valid 1 npu_result channel tx: a buffered result is ready to send
in res_tx_ready 1 Channel credit available
out res_tx_data 32 Buffered accumulator value
out res_tx_tag 4 Buffered accumulator row index

Functionality

Dispatch passthrough: npu_valid_w = disp_rx_valid, disp_rx_ready = npu_ready_w. The flit is only popped — and channel credit returned to the base die — on the exact cycle the NPU actually accepts it (i.e. when npu is IDLE), reproducing the original noc_router ↔ npu handshake unchanged across the die boundary, plus the fixed 2-cycle crossing latency.

Result draining: the NPU's result_valid/result_index/result_data bus is drained into a local 16-entry FIFO (one slot per accumulator row) as fast as npu produces it (result_ready_w = !res_fifo_full), fully decoupling the compute pipeline's OUTPUT_ST timing from the UCIe link's own latency/credit. A small drain FSM (really just FIFO push/pop counters) streams the buffered results out over res_tx_* at whatever pace res_tx_ready allows.

Example

For one COMPUTE, all 16 rows land in the FIFO essentially back-to-back (one per cycle, OUTPUT_ST), then drain out over the link independently:

OUTPUT_ST cycle r: npu.result_valid=1, result_index=r, result_data=acc[r][31:0]
                    -> res_push (FIFO write, res_wr_ptr++)
res_tx side:        res_tx_valid=1 whenever FIFO non-empty
                    -> res_pop on res_tx_ready (base die's chan_npu_result credit)

If the NPU produces results faster than the base die can drain them (link momentarily out of credit), the FIFO absorbs the burst — this is why chan_npu_result in system_top.sv is sized DEPTH=4, not 1.

  • npu.md — the unmodified compute core instantiated here as npu_inst
  • chiplets.md — NPU-link handshake writeup, flit table
  • ucie_chan.md — the channel this FIFO feeds