RTL Source Reference

One page per file in rtl/, each with its port list, functionality, and worked examples. This is the file-level companion to the narrative design docs (architecture.md, chiplets.md, cpu.md, npu.md, gpu.md) — those explain how the pieces fit together; these pages document each file on its own.

Chip assembly & chiplets (v5)

File	Role
system_top.sv	Chip boundary — package assembly of the three dies
base_die_top.sv	Base/I-O die: NoC router, MOESI L2, GPU, external I/O
cpu_chiplet_top.sv	CPU chiplet: riscv_core + imem + halt detect
npu_chiplet_top.sv	NPU chiplet: npu + result buffering

UCIe transport

File	Role
ucie_chan.sv	Generic unidirectional channel: credit flow control + crossing latency
ucie_link_ctrl.sv	Link training FSM (functional stub)
duck_ucie_pkg.sv	Flit field/opcode reference (docs-only, not imported)

Routing

File	Role
noc_router.sv	Live 3-port opcode router (CPU/GPU/NPU)
server_dispatch_unit.sv	Historical predecessor of noc_router.sv — not instantiated

CPU datapath

File	Role
riscv_core.sv	RV32IM 5-stage pipeline
alu.sv	Integer ALU: base ops + MUL (3-cy) + DIV (34-cy)
imm_decode.sv	RV32 immediate extractor (I/S/B/U/J)
register_file.sv	32×32-bit register file

Memory / coherency

File	Role
duck_coherency_ctrl.sv	Live 2-master MOESI L2 cache + coherency FSM
l2_cache.sv	Historical single-master predecessor — not instantiated
duck_cache_pkg.sv	MOESI type/geometry reference (docs-only, not imported)

Compute accelerators

File	Role
npu.sv	16×16 MAC array — INT8/INT16, ping-pong weight banks, tiled GEMM
pe.sv	Systolic MAC-cell architectural reference — not instantiated
gpu.sv	16-lane INT32 vector ALU (ADD/SUB/AND/XOR)

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Currently instantiated in the live build (i.e. reachable from system_top): system_top, base_die_top, cpu_chiplet_top, npu_chiplet_top, ucie_chan, ucie_link_ctrl, noc_router, riscv_core, alu, imm_decode, register_file, duck_coherency_ctrl, npu, gpu — 14 files, matching Makefile's VERILOG_SOURCES list. server_dispatch_unit, l2_cache, and pe are historical/reference-only; duck_ucie_pkg and duck_cache_pkg are docs-only packages never imported (Icarus Verilog 11 / cocotb 2.0 compatibility — flat signals only on module ports).

See tb/index.md for the testbench-side reference, and verification.md for how to run everything.