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Queue for the 5-hourly automation. Checked = eligible — the topmost checked item runs next. Uncheck to hold/skip an item (edit this file, or toggle on the Status page when the site is served via scripts/serve_site.py). The automation removes completed items, preserves your holds, and appends new suggestions checked by default.

Roadblocked items are not queued here — they're parked in docs/unsolved/ until a human fixes them on a branch. Currently: UNSOLVED-001 (MOESI DMA flush, BUG-006).

Queue

  • Wireless peripheral driver — package NPU result frames and transmit to remote displays (currently a no-op port)
  • Multi-word NPU DMA — burst-load a full weight tile (256 words) per DMA transaction
  • Formal verification of MOESI FSM — SymbiYosys: no deadlock; npu_dma_ack pulses exactly once per request
  • GPU vector ALU: more ops — v1 covers ADD/SUB/AND/XOR; add OR, shifts, and min/max/compare

Last run

2026-07-21 — GPU / AIPU internal micro-architecture — minimum viable 16-lane INT32 vector ALU (ADD/SUB/AND/XOR), completing the item that had been sitting checked at the top of the queue since it was scheduled for 2026-07-20 20:00 — that run and every 5-hourly run since never actually fired (cron never produced a single log line; see automation/guard.sh fixes below), so this was done as a manual catch-up run in its place.

  • New rtl/gpu.sv: 16-lane parallel INT32 vector ALU (LOAD_A/LOAD_B/COMPUTE/NOP, opcode 0x57). vec_a/vec_b persist across instructions.
  • rtl/noc_router.sv: GPU port restored (3rd port; was CPU+NPU only since v3) — custom-0 now routes to GPU.
  • rtl/base_die_top.sv / rtl/system_top.sv: GPU instantiated directly on the base die (no UCIe crossing for this MVP); new gpu_result_* bus forwarded to system_top.
  • 4 new tests in tb/tb_server_dispatch_unit.py (run_gpu_vector_add, _sub, _bitwise, _random_reload). Full regression: TESTS=15 PASS=15 FAIL=0. MOESI suite unchanged (1 PASS / 2 FAIL, BUG-006 still open, confirmed unrelated).
  • Docs: gpu.md (new), todo.md, progression.md, verification.md, README.md, mkdocs.yml nav.
  • Fixed two bugs in automation/guard.sh found while diagnosing why the schedule hadn't run: date -d 'monday this week' returns the next Monday (not the most recent one) when today isn't Monday, so the weekly-cap window was silently wrong; and cron's minimal PATH doesn't include ~/.local/bin, where the claude CLI lives, so the automated invocation of claude -p would never resolve under cron even though the crontab entry itself was correct. guard.sh now computes week_start from the ISO weekday and exports an explicit PATH including $HOME/.local/bin.

2026-07-20 — Added the Unsolved log: pulled "Fix BUG-006" out of the queue above and logged it as UNSOLVED-001 — it had already gone unsolved through two runs (found 2026-07-19, re-attempted and still unresolved 2026-07-20) without new information, so it's parked for a human to investigate on a branch rather than keep retrying it unattended every 5 hours. automation/dev_cycle.md now checks that log before picking a queue item, and routes future roadblocks there instead of leaving them silently unfinished in the queue.

2026-07-20 — Chiplet disaggregation + UCIe (user-directed, out of queue order).

  • Split system_top into three dies connected by modeled UCIe links: base_die_top.sv (NoC router + MOESI L2 + external I/O), cpu_chiplet_top.sv (riscv_core + imem + halt), npu_chiplet_top.sv (npu + result buffering). New support RTL: ucie_chan.sv (credit-based flow control + crossing latency), ucie_link_ctrl.sv (link training FSM), duck_ucie_pkg.sv (flit reference, docs only). system_top's external port list is unchanged; full writeup at chiplets.md.
  • noc_router.sv, duck_coherency_ctrl.sv, riscv_core.sv, and npu.sv are all unmodified — every new file is a bridge/wrapper.
  • BUG-007 (found and fixed): splitting network ingestion from CPU stall cycles (cpu_ready is now UCIe channel credit, not !core_stall) let the fetch pointer race ahead to the halt word while a chained remu t3, s1, s2 / remu t4, s5, s1 pair was still retiring, so halt fired ~24 cycles early and t3 read back as 0 instead of 1. Fixed by gating halt on !core_stall in cpu_chiplet_top.sv and raising HALT_DRAIN_CYCLES 10 → 40 in tb/tb_server_dispatch_unit.py for the remaining one-op race window. See docs/issues/BUG-007.md.
  • Testbench updates: hierarchical register-file paths (dut.cpu_core_inst... → dut.cpu_chiplet_inst.cpu_core_inst...), five new sources added to Makefile's VERILOG_SOURCES.
  • Full tb_server_dispatch_unit regression: TESTS=11 PASS=11 FAIL=0 (matches pre-split baseline). MOESI integration: 1 PASS / 2 FAIL, unchanged — confirmed BUG-006 is pre-existing and unrelated to this session's changes.

2026-07-19 — Fixed run_riscv_program (user-directed, out of queue order).

  • BUG-004: rtl/system_top.sv was calling $finish directly from RTL 20 cycles after halt, racing cocotb's own end-of-regression shutdown and causing SimFailure: Simulator shut down prematurely on every run. Removed the block — simulation lifecycle now belongs entirely to cocotb, as it already did for every other test in the suite.
  • BUG-005: with BUG-004 fixed, the sim ran to completion and exposed a second, independent bug: tb/cpu_peak_tests.asm's remu t4, s5, s1 check asserted t4==55, but 88560 % 205 is actually 0 (205×432=88560 exactly; the comment's 205×431+55=88410 arithmetic was wrong). Corrected the expected value.
  • Full tb_server_dispatch_unit regression: TESTS=11 PASS=11 FAIL=0.
  • While verifying, also ran the MOESI suite as a sanity check and found TC-MOESI-1/TC-MOESI-2 failing with BUG-003's exact symptom even though BUG-003's fix (ST_NPU_GAP) is present in the code. Confirmed via git stash that this predates this session's changes — filed as BUG-006 (open) rather than fixed here, since it's unrelated to the run_riscv_program scope of this run.