Testbench Reference
One page per file in tb/, each covering what it drives, its test list, and how to run it. Companion to verification.md (the current pass/fail dashboard across all suites) and rtl/index.md (the file-level RTL reference these tests exercise).
| File | Tests | Status | Covers |
|---|---|---|---|
| tb_server_dispatch_unit.py | 15 | 15 PASS / 0 FAIL | Main regression: NPU (10), GPU (4), full RV32IM CPU program (1) |
| tb_moesi_integration.py | 3 | 1 PASS / 2 FAIL — BUG-006 | MOESI coherency: CPU-dirty-line flush on NPU DMA read |
| tb_video_stream_workload.py | 2 | 2 PASS / 0 FAIL | 256 kbps video-stream workload: CPU+NPU sustained throughput & concurrency |
Total: 20 tests, 18 PASS / 2 FAIL (the 2 failures are the pre-existing, tracked UNSOLVED-001 MOESI issue, unrelated to the other two suites).
Shared conventions across all three files
- Every test drives
system_top(see rtl/system_top.md) — none instantiate a sub-module directly. - Every instruction dispatch goes through the same
net_valid/net_ready/net_instructionhandshake (send_instruction()), regardless of which engine (CPU/GPU/NPU) it targets — the NoC router does the routing, not the testbench. tb_moesi_integration.pyandtb_video_stream_workload.pyboth build ontb_server_dispatch_unit.py's primitives rather than re-deriving them — the latter via a direct Python import (from tb_server_dispatch_unit import ...), the former by re-declaring an equivalent local copy (predates the shared-import convention).- CPU register assertions all reach into the same hierarchical path:
dut.cpu_chiplet_inst.cpu_core_inst.rf_unit.rf[i].
Running everything
./run_sims.command # MOESI + regression suites, one shot
make MODULE=tb_video_stream_workload # the new workload suite
See verification.md for the full runnable-command reference (Docker vs. local toolchain, single-test selection, etc.).