Server Dispatch Unit (SDU)

The SDU (rtl/server_dispatch_unit.sv) is the central hardware router of the SoC. It decodes the 7-bit opcode in a single combinational cycle and drives the appropriate valid/ready signals to the target engine.

Responsibilities

Classify — extract opcode = net_instruction[6:0]
Route — assert cpu_valid, gpu_valid, or npu_valid to the correct engine
Backpressure — deassert net_ready when the target is busy
Accept pulse — generate cpu_accept (one-cycle combinational pulse) to trigger SRAM writes

Opcode Routing Table

Opcode `[6:0]`	RISC-V class	Target engine
`0x37` LUI	U-type	CPU
`0x17` AUIPC	U-type	CPU
`0x6F` JAL	J-type	CPU
`0x67` JALR	I-type	CPU
`0x63` BRANCH	B-type	CPU
`0x03` LOAD	I-type	CPU
`0x23` STORE	S-type	CPU
`0x13` ALU-IMM	I-type	CPU
`0x33` ALU-REG (incl. MUL)	R-type	CPU
`0x57`	custom-0 / RVV	GPU / AIPU
`0x6B`	custom-1	NPU v2
anything else	—	dropped (no route)

Handshake Protocol

The SDU sits between the network source (upstream) and three engines (downstream). All interfaces use valid/ready handshakes.

Network source
  net_valid ──────────────────────────────────────────► SDU
  net_ready ◄────────────────────────────────────────── SDU
  net_instruction ─────────────────────────────────────► SDU

SDU → CPU
  cpu_valid ───────────────────────────────────────────► riscv_core
  cpu_ready ◄──────────────────────────────────────────── system_top
  cpu_instruction ─────────────────────────────────────► system_top

SDU → GPU
  gpu_valid ───────────────────────────────────────────► GPU interface
  gpu_ready ◄──────────────────────────────────────────── GPU interface
  gpu_instruction ─────────────────────────────────────► GPU interface

SDU → NPU
  npu_valid ───────────────────────────────────────────► npu
  npu_ready ◄──────────────────────────────────────────── npu (IDLE only)
  npu_instruction ─────────────────────────────────────► npu

net_ready is deasserted as long as the target engine is not ready:

assign net_ready = (target_cpu & cpu_ready)
                 | (target_gpu & gpu_ready)
                 | (target_npu & npu_ready);

The `cpu_accept` Pulse

The SDU generates cpu_accept — a one-cycle combinational pulse — when a CPU instruction is accepted on the network handshake:

assign cpu_accept = target_cpu & route_valid & net_ready;

route_valid is high when net_valid is asserted and the opcode maps to a known engine.

system_top uses this pulse to write net_instruction directly into the instruction SRAM at the current write pointer, then increments the pointer:

always_ff @(posedge clk) begin
    if (cpu_accept) begin
        imem[imem_wr_ptr] <= net_instruction;
        imem_wr_ptr       <= imem_wr_ptr + 1;
    end
end

This guarantees each accepted instruction is stored exactly once, regardless of how long cpu_valid stays asserted during MUL stalls or back-to-back loading.

Backpressure Scenarios

Scenario	Effect
CPU executing MUL (`core_stall=1`)	`cpu_ready=0` → `net_ready=0` → source stalls
NPU in COMPUTE/LOAD/OUTPUT (`npu_ready=0`)	`net_ready=0` → source stalls
GPU busy	`gpu_ready=0` → `net_ready=0` → source stalls
Unknown opcode	No target asserted → `net_ready=0` → instruction dropped

Implementation Notes

All routing logic is purely combinational — no registers in the SDU itself.
cpu_instruction and npu_instruction are wired directly from net_instruction (pass-through). The SDU does not buffer or transform the instruction payload.
The always_ff block handles any registered SDU signals (currently minimal — the SDU is intentionally stateless).