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rtl/base_die_top.sv — Base / I-O Die

Owns everything that touches the outside of the package: network ingress (noc_router), the MOESI L2 + coherency controller (duck_coherency_ctrl, talking to external DRAM and the NPU DMA port), and the GPU (gpu, instantiated directly here — no UCIe crossing for this minimum-viable version). Mirrors real chiplet packages (AMD CCD/IOD, Intel tile splits) where compute dies stay "dumb" from an I/O standpoint and a single base die aggregates shared memory and all external I/O. See chiplets.md for the full rationale.

Where it fits

Instantiated once by system_top.sv as base_die_inst. Talks to cpu_chiplet_top over the CPU link (instr_load/mem_req/mem_rsp) and npu_chiplet_top over the NPU link (npu_disp/npu_result), both via ucie_chan instances that live in system_top.

Ports

Direction Name Width Description
in clk, rst_n 1, 1 Clock / reset
in/out net_valid/net_ready/net_instruction 1/1/32 Top-level network interface, passed straight to noc_router
out/in npu_result_* — Forwarded from res_rx_* (NPU link rx) to the top-level result bus
out/in gpu_result_* — Direct from the locally-instantiated gpu
in/out npu_dma_* — Passed straight to duck_coherency_ctrl
out/in dram_* — Passed straight to duck_coherency_ctrl
out/in ld_tx_* 1/1/32 CPU link tx: instr_load channel (base → cpu)
in/out mreq_rx_* 1/1/4/32/32/4 CPU link rx: mem_req channel (cpu → base)
out/in mrsp_tx_* 1/1/32 CPU link tx: mem_rsp channel (base → cpu)
out/in disp_tx_* 1/1/32 NPU link tx: npu_disp channel (base → npu)
in/out res_rx_* 1/1/32/4 NPU link rx: npu_result channel (npu → base)

Functionality

CPU link bridging: - ld_tx_valid = cpu_accept — the router's existing single-cycle accept pulse fires the instr_load send directly; cpu_ready (router's own input) is now the channel's credit (ld_tx_ready) instead of !core_stall. This is the change that decouples network ingestion from CPU internal MUL/DIV stalls — see BUG-007. - A small mreq/mrsp bridge FSM (BREQ_IDLE → BREQ_ACTIVE → BREQ_SEND) stands in for "riscv_core" from duck_coherency_ctrl's point of view: latches the incoming request, holds cpu_read/write/addr/wdata/byte_en until cpu_stall (aliased l2_stall) clears, then sends the response as a single mrsp flit.

NPU link bridging: disp_tx_valid = npu_valid_int (router's held dispatch register, forwarded as-is); npu_ready_int = disp_tx_ready (channel credit). res_rx_* is forwarded directly onto npu_result_valid/index/data, res_rx_ready = npu_result_ready.

GPU: wired directly to the router's restored GPU port — no UCIe crossing, unlike the NPU.

noc_router.sv and duck_coherency_ctrl.sv are both instantiated here unmodified.

Example

The CPU-link bridge FSM's three states, one instruction round-trip:

BREQ_IDLE   — mreq_rx_valid arrives; latch addr/wdata/byte_en/we, -> BREQ_ACTIVE
BREQ_ACTIVE — drives cpu_mem_read/write into duck_coherency_ctrl; waits for !l2_stall
BREQ_SEND   — mrsp_tx_valid=1, sends the captured cpu_mem_rdata back; waits mrsp_tx_ready
            -> BREQ_IDLE