Skip to content

BUG-002: Duplicate HALT_WORD send race condition

Field Value
Severity HIGH
Component Testbench
File(s) tb/tb_server_dispatch_unit.py — run_riscv_program()
Status Fixed
Date 2025-06

Symptom

Tests using run_riscv_program() with programs containing DIV/DIVU instructions (34-cycle stall) intermittently raised SimFailure. The failure was timing-sensitive and did not appear in shorter or arithmetic-only programs.

Root Cause

Two sources of HALT_WORD (jal x0,0 = 0x0000006F) were sent for every program:

  1. The assembly file itself ends with jal x0,0 (the intended halt sentinel).
  2. run_riscv_program() explicitly sent HALT_WORD a second time after the loading loop (lines 751–752).

This injected a second jal x0,0 into imem[N+1]. During 34-cycle DIV stalls, the CPU pipeline could fetch imem[N+1] before the stall froze the PC, triggering an extra halt detection that confused the drain/completion logic and caused SimFailure.

Fix

Remove the explicit HALT_WORD send from run_riscv_program(). The halt sentinel is now provided solely by the final jal x0,0 in each .asm file.

  # after loading loop
- dut.net_valid.value       = 1
- dut.net_instruction.value = HALT_WORD   # redundant — already in .asm
  dut.net_valid.value = 0

Notes

Every .asm file used with run_riscv_program() must already end with jal x0,0. The duplicate was a historical artifact from an earlier testbench version where the assembly files did not self-terminate.