Digital Design Engineer
Karthik Mahendra
I build RTL, verify it, and take it to silicon — from CDC-safe FIFOs to full ASIC tapeouts. This is where that work lives.
Featured Projects
ACORN Authenticated Encryption Cipher
Verilog implementation of the ACORN128 authenticated encryption cipher — a hardware security primitive built from the state machine up.
16-bit Neuron Unit with ReLU Activation
A building block for hardware neural networks — 16-bit MAC datapath with a ReLU activation function in RTL.
Verilog Fundamentals — Gate to RTL
A working set of Verilog exercises spanning basic gates, adders, muxes, a UART receiver, and a high-performance ALU.
eSim Circuit Library
A library of foundational circuits in eSim — logic gates, adders, a 555 timer, and Wallace tree multipliers from 2- to 8-bit.
Machine Learning Notebooks
Applied ML notebooks covering regression, classification, and a house-price prediction project end to end.
Recent Activity
Jun 15, 2025
Most common RTL Bugs and How they are Fixed
Mar 29, 2024
LED Chaser circuit with KiCAD at Purdue's Design Studio
Oct 27, 2023
Breathing Life Back into TI-83 Calculators Through Soldering
Sep 5, 2022
The Abated Invention Found Its Way Creating Electronic History
Aug 26, 2022
Penn State and U.S Air Force researchers have engineered a novel material that can now ‘think’
Jul 8, 2021
Steps to Implement a 3-bit Wallace Tree Multiplier using SKY130 PDK and eSim