cdc_fifo_sync.v / sim_vcd

// Gray Code Sync Stage
assign wptr_gray = wptr ^ (wptr >> 1);

always @(posedge rclk) begin
  // 2-stage sync to Fast Clock
  wptr_s1 <= wptr_gray;
  wptr_s2 <= wptr_s1;
end

assign rempty = (wptr_s2 == rptr);

DOMAIN_CROSS: SLOW_TO_FAST

WCLK WDATA RCLK RDATA

METASTABILITY_GUARD: ACTIVE

Welcome to my little corner of the internet, where I code, create, and sometimes accidentally break things. The blog covers hardware articles, how-to’s, workshops experiences, and electronic designs.

Here, you’ll find my portfolio, a byte of my journey, and hopefully a bit of inspiration for your next project.

Hope you enjoy what you’re reading here!

Achievements

Event	Result	Context
IEEE HKN Hackathon	5th Place	Int’l Founders Day Hackathon [Cert]
Capture the Bug	Top 52	National Design Verification Hackathon [Repo]
eSim Marathon	1st Place	Winner out of 600+ submissions [Cert]

Highlights

INITIALIZING...

ARCH: QARBYTE-CORE // STATUS: ACTIVE_TRACE

01 / 08

Highlights & Workshops

• Speaker & Workshop Instructor, “Sand to Silicon: Build Your Custom ASICs”, Purdue University.
• ECE Department Internship Instructor, Purdue University.
• PCB Design Workshop Instructor, Design Studio at Purdue University (March 29th, October 25th 2024)
• Member of Institute of Electrical and Electronics Engineers (IEEE) [Profile]

Technical Papers & Research

Year	Technical Deep-Dive	Format
2025	Wireless Channel Modelling at Propagation Scenarios	[PDF]
2024	Two-Level Branch Predictor Design	[PDF]
2024	Base-Base Conversion Tool (MATLAB)	[PDF]
2023	IP Geolocation using Traceroute	[PDF]
2023	Kalman Filter for State Estimation	[PDF]
2019	Design of UART Receiver Protocol	[PDF]
2019	House Sale Prediction via Linear Regression	[PDF]
2018	Green Chips - The Tech That Made World Smaller	[PDF]