Github
All the links direct to github files or reporsitories
Hardware for ACORN Encryption/Decryption cipher algorithm
- An implementation of the ACORN authenticated encryption cipher in Verilog. A cryptographic design showcasing hardware security principles.
16-bit Neuron Unit with ReLU Activation
- The fundamental building block of an artificial neural network, using a 16-bit ReLU activation function. A step toward hardware implementations of machine learning.
AI Powered Solar panel monitor Hardware design
- This RTL block implements an AI-powered solar panel monitor. It takes the voltage, current, and temperature readings from the solar panel as inputs, and calculates the power and efficiency of the solar panel. The results are then displayed on an external display.
RTL to GDS for a Modified 8-bit Dadda Multiplier using 3:2 Compressors with sky130 PDK and OpenLane
- A modified Dadda multiplier uses 3:2 compressors to further reduce the speed and improve the efficiency of the design. The multiplier design uses two 8-bit inputs(A and B) to produce a 16-bit output.
Design of Inter Integrated Circuit I2C in Verilog
- RTL for I2C controller in verilog, passed through OpenLANE flow to generate GDS II
Schematic design of Wallace tree multiplier using SKY130 PDK in eSim]
- A Wallace multiplier is a digital circuit which multiplies two integers in binary format. It uses half and full adders to sum partial products in stages until two numbers are left.
Logging Fundamental Parameters of Plants with Raspberry-Pi
- This project is built using Raspberry Pi which acts as a Gardener collecting sensor data and computing accordingly.
Verilog Design Projects
- Basic Gates: AND, OR, NAND, NOR, XOR, XNOR [code]
- 1-Bit Inverter [code]
- Half Adder [code]
- Pulse Width Modulation (PWM) [repo]
- 8-bit Numerically Controlled Oscillator [repo]
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Universal Asynchronous Receiver-Transmitter (UART) Receiver [code]
- 16-Bit Binary Adder Tree [code]
- 1-Bit Full Adder [code]
- Building block for any binary arithmetic operation.
- 2:1 Multiplexer
- A simple 2:1 MUX, essential for data routing in digital systems.
- Cilantro RISC-V Processor [repo] (In Progress)
- Focus on hardware implementation of RISC-V with minimalistic architecture.
- MIPS Processor [repo] (In Progress)
- 16-bit Neuron Unit with ReLU Activation [repo]
- Simon 32/64 Cipher [code]
- Ripple carry adder testbench [code]
- Universal Shift register - DUT, TB
- FNN - Example neural network [code], [TB]
- High performance ALU [code]
- VLSI Design through verilog part 1 [pdf]: 4 X 1 Multiplexer, Full Adder, 4 bit UP/DOWN Counter
- VLSI Design through verilog part 2 [pdf]: Verilog code for an ALU, Decoder, 4×2 Multiplexer using 2×1 mux, Parity Checker, Encoder
Schematic and PCB Designs
- Digital Gates circuit AND , OR , XOR , Inverter
- Half adder circuit [repo]
- Full adder circuit [repo]
- 555 Timer circuit [repo]
- Wallace Tree multiplier circuits 2 bit , 3 bit , 4 bit , 8 bit
- Breadboard power supply [repo]
- Raspberry Pi FS Hat v01 [repo]
- Arduino Battery Powered clone with extended EEPROM and clock [repo]
- Op Amp Logarthmic amplifier [repo]
- DC to DC converter [repo]
- Gouriet clapp capacitive three point oscillator [repo]
- Decimal counter [repo]
Hardware Programming
Python and Machine Learning
- Beginner to Intermediate Programming in Python [notebook]
- Machine Learning with Python [notebook]
- Project: House Sale Price Prediction using Linear Regression [Jupyter notebook]
Learning Resources & References
For those new to Verilog or looking for deeper insights.
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Data Types in Verilog HDL [code]
A primer on Verilog data types, essential for anyone working with hardware description languages. -
Code Questions on Data Types [doc]
Exercises to test your understanding of Verilog data types. -
Icarus Verilog + GTK Wave Guide [pdf]
Learn how to simulate and visualize your Verilog designs with Icarus Verilog and GTK Wave.
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Memory maps for engineering concepts: Antennas Classification , Computer Networks , Cryptography , Modern Communication , Evolution of Semiconductor , microwave Devices
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OpenRAM Configuration for 4kB SRAM using sky130 [doc]
Get Involved
Feel free to explore the projects, contribute, or ask questions. Your feedback and contributions are always welcome. If you have any queries or want to collaborate on a project, don’t hesitate to reach out!